Today, I had an opportunity to host Professor Rajit Manohar from Cornell University. He gave us an amazing talk.
Ultra Low Power Asynchronous VLSI
We present the design of SNAP: an ultra low power asynchronous processor optimized for embedded sensing applications. The circuit style used by SNAP has been optimized for both area and energy to enable the development of a small, long lifetime sensor node. The asynchronous nature of the processor enables efficient transitions from idle to active back to idle state. We present measured performance and energy results for our design. In 0.18um, typical monitoring tasks can be performed with a power budget of 0.6uW.
We will also provide a brief introduction of asynchronous design methodologies, and their relation to concurrent program development.
Ph.D. Computer Science, Caltech (1998); Leader in asynchronous VLSI design; inventor of GHz-speed FPGA technology and ultra low power processors; ~10 issued patents and >50 published papers; MIT Technology Review TR35 awardee; Founder and Chief Technology Officer, Achronix Semiconductor Corp.